Communications networks continue to grow in breadth of coverage and data density. An important enabling technology of this continued growth is increased integration of optical (photonic) components. For example, metropolitan area networks and wide area networks are now being deployed with wavelength division multiplexing (WDM) which add/drop channels using wavelength selective filters integrated onto silicon, or other semiconductor, substrates using very large scale integration (VLSI) manufacturing techniques.
In certain applications, for example where an IOC chip is an optical transceiver, a lens or other optical interconnect (e.g., optical fiber) is mechanically assembled onto an IOC chip. Once the lens is attached, a jumper connector or similar mechanical coupling may be attached to create an optical link, for example with optical fibers.
Component placement, bonding, lens alignment and attachment are time-consuming and cumbersome processes, each associated with a manufacturing tolerance. For example, in one conventional method, an IOC chip is placed on a substrate and then, using a pick and place machine with a visual aligning system, the mechanical coupling is aligned and placed on the chip.
With conventional assembly techniques, there are significant amounts of positional deviation (e.g., tolerance stack) between the mechanical coupling and the IOC chip. Positional deviation can induce performance issues and even render a packaged IOC inoperable, requiring rework or scrap of the photonic device assembly. For both techniques, alignment frame variation, placing capability (IOC chip and/or alignment frame), and mechanical coupling variation all contribute to the positional deviation.